#ifndef _SI24R1_H
#define _SI24R1_H
#pragma anon_unions
#include "stdint.h"
// SPI(SI24R1) commands
#define NF_READ_REG        0x00  // Define read command to register
#define NF_WRITE_REG       0x20  // Define write command to register
#define RD_RX_PLOAD     0x61  // Define RX payload register address
#define WR_TX_PLOAD     0xA0  // Define TX payload register address
#define FLUSH_TX        0xE1  // Define flush TX register command
#define FLUSH_RX        0xE2  // Define flush RX register command
#define REUSE_TX_PL     0xE3  // Define reuse TX payload register command
#define NOP             0xFF  // Define No Operation, might be used to read status register
//********************************************************************************************************************//
// SPI(SI24R1) registers(addresses)
#define CONFIG          0x00  // 'Config' register address
#define EN_AA           0x01  // 'Enable Auto Acknowledgment' register address
#define EN_RXADDR       0x02  // 'Enabled RX addresses' register address
#define SETUP_AW        0x03  // 'Setup address width' register address
#define SETUP_RETR      0x04  // 'Setup Auto. Retrans' register address
#define RF_CH           0x05  // 'RF channel' register address
#define RF_SETUP        0x06  // 'RF setup' register address
#define STATUS          0x07  // 'Status' register address
#define OBSERVE_TX      0x08  // 'Observe TX' register address
#define RSSI          0x09  // 'Received Signal Strength Indecator' register address
#define RX_ADDR_P0      0x0A  // 'RX address pipe0' register address
#define RX_ADDR_P1      0x0B  // 'RX address pipe1' register address
#define RX_ADDR_P2      0x0C  // 'RX address pipe2' register address
#define RX_ADDR_P3      0x0D  // 'RX address pipe3' register address
#define RX_ADDR_P4      0x0E  // 'RX address pipe4' register address
#define RX_ADDR_P5      0x0F  // 'RX address pipe5' register address
#define TX_ADDR         0x10  // 'TX address' register address
#define RX_PW_P0        0x11  // 'RX payload width, pipe0' register address
#define RX_PW_P1        0x12  // 'RX payload width, pipe1' register address
#define RX_PW_P2        0x13  // 'RX payload width, pipe2' register address
#define RX_PW_P3        0x14  // 'RX payload width, pipe3' register address
#define RX_PW_P4        0x15  // 'RX payload width, pipe4' register address
#define RX_PW_P5        0x16  // 'RX payload width, pipe5' register address
#define FIFO_STATUS     0x17  // 'FIFO Status Register' register address

//********************************************************************************************************************//
// STATUS Register 
//#define RX_DR		    0x40  /**/
//#define TX_DS			0x20
//#define MAX_RT		    0x10

/********************
 * 配置寄存器
 * *****************/
typedef union {
	struct {
		uint8_t PRIM_RX:1;
		uint8_t PWR_UP:1;
		uint8_t CRCO:1;
		uint8_t EN_CRC:1;
		uint8_t MASK_MAX_RT:1;
		uint8_t MASK_TX_DS:1;
		uint8_t MASK_RX_DR:1;
		uint8_t :1;
	};
	uint8_t reg;
} Config_Regist;
/********************
 * 使能自动确认
 * *****************/
typedef union {
	struct {
		uint8_t ENAA_P0:1;
		uint8_t ENAA_P1:1;
		uint8_t ENAA_P2:1;
		uint8_t ENAA_P3:1;
		uint8_t ENAA_P4:1;
		uint8_t ENAA_P5:1;
		uint8_t :2;
	};
	uint8_t reg;
} ENAA_Regist;
/********************
 * 使能接收数据管道地址
 * *****************/
typedef union {
	struct {
		uint8_t ERX_P0:1;
		uint8_t ERX_P1:1;
		uint8_t ERX_P2:1;
		uint8_t ERX_P3:1;
		uint8_t ERX_P4:1;
    uint8_t ERX_P5:1;
    uint8_t :2;    
	};
	uint8_t reg;
} EN_RXADDR_Regist;
/********************
 * 地址宽度配置
 * *****************/
typedef union {
	struct {
		uint8_t AW:2;
		uint8_t :6;
	};
	uint8_t reg;
} SETUP_AW_Regist;

/********************
 * 自动重发配置
 * *****************/
typedef union {
	struct {
		uint8_t ARC:4;      //最大自动重发次数
		uint8_t ARD:4;      //自动重发延时配置
	};
	uint8_t reg;
} SETUP_RETR_Regist;
/********************
 * 地址宽度配置
 * *****************/
typedef union {
	struct {
		uint8_t RF_PWR:3;    //设置射频发射功率
		uint8_t RF_DR:3;     //设置射频数据率
		uint8_t :1;
		uint8_t CONT_WAVE :1;
	};
	uint8_t reg;
} RF_SETUP_Regist;

/********************
 * 地址宽度配置
 * *****************/
typedef union {
	struct {
		uint8_t TX_FULL:1;  //TX FIFO为空
		uint8_t RX_P_NO:3;  //收到数据的接收管道PPP号，可以通过SPI读出  000-101：数据管道0-5  110：不可用  111：RX FIFO为空
		uint8_t MAX_RT:1;   //达到最大重发次数中断位，写"1"清除
		uint8_t TX_DS:1;    //发射端发射完成中断位，如果时ACK模式，则收到ACK确认信号TX_DS位置1，写"1"清楚
		uint8_t RX_DR:1;    //RX FIFO有值标志位，写“1"清除
		uint8_t :1;    
	};
	uint8_t reg;
} STATUS_Regist;

/********************
 * 发射结果统计
 * *****************/
typedef union {
	struct {
		uint8_t ARC_CNT:4;    //重发计数  发射一个新包时，ARC_CNT从0开始计数
		uint8_t PLOS_CNT:4;   //丢包计数  最大计数为15，改变RF_CH后从0开始计数
	};
	uint8_t reg;
} OBSERVE_TX_Regist;

/********************
 * 接收信号强度检测
 * *****************/
typedef union {
	struct {
		uint8_t rssi:1;
		uint8_t :7;
	};
	uint8_t reg;
} RSSI_Regist;

/********************
 * 接收数据管道0数据字节数
 * *****************/
typedef union {
	struct {
		uint8_t RX_PW:6;
		uint8_t :2;
	};
	uint8_t reg;
} RX_PW_P0_Regist;

/********************
 * 接收数据管道1数据字节数
 * *****************/
typedef union {
	struct {
		uint8_t RX_PW:6;
		uint8_t :2;
	};
	uint8_t reg;
} RX_PW_P1_Regist;
/********************
 * 接收数据管道2数据字节数
 * *****************/
typedef union {
	struct {
		uint8_t RX_PW:6;
		uint8_t :2;
	};
	uint8_t reg;
} RX_PW_P2_Regist;

/********************
 * 接收数据管道3数据字节数
 * *****************/
typedef union {
	struct {
		uint8_t RX_PW:6;
		uint8_t :2;
	};
	uint8_t reg;
} RX_PW_P3_Regist;

/********************
 * 接收数据管道4数据字节数
 * *****************/
typedef union {
	struct {
		uint8_t RX_PW:6;
		uint8_t :2;
	};
	uint8_t reg;
} RX_PW_P4_Regist;
/********************
 * 接收数据管道5数据字节数
 * *****************/
typedef union {
	struct {
		uint8_t RX_PW:6;
		uint8_t :2;
	};
	uint8_t reg;
} RX_PW_P5_Regist;


/********************
 * FIFO状态
 * *****************/
typedef union {
	struct {
		uint8_t RX_EMPTY:1;    //RX FIFO空标志  1：空 0：有数据
		uint8_t RX_FULL:1;     //RX FIFO满标志  1：满 0：可写
		uint8_t :2;
		uint8_t TX_EMPTY:1;    //TX FIFO空标志  1：空 0：有数据
		uint8_t TX_FULL:1;     //TX FIFO满标志  1：满 0：可写
		uint8_t TX_REUSE:1;    //只用于发送端，FIFO数据重新利用，当用RESUSE_TX_PL命令后，发送上次已成功发送的数据
		uint8_t :1;
	};
	uint8_t reg;
} FIFO_STATUS_Regist;
/********************
 * 使能动态长度
 * *****************/
typedef union {
	struct {
		uint8_t DPL_P0:1;     //使能接收管道0动态负载长度
		uint8_t DPL_P1:1;     //使能接收管道5动态负载长度
    uint8_t DPL_P2:1;     //使能接收管道4动态负载长度
    uint8_t DPL_P3:1;     //使能接收管道3动态负载长度
    uint8_t DPL_P4:1;     //使能接收管道2动态负载长度
    uint8_t DPL_P5:1;     //使能接收管道1动态负载长度
		uint8_t :2;
        
	};
	uint8_t reg;
} DYNPD_Regist;
/********************
 * 特征寄存器
 * *****************/
typedef union {
	struct {
		uint8_t EN_DYN_ACK:1;    //使能命令W_TX_PAYLOAD_NOACK
		uint8_t EN_ACK_PAYd:1;   //使能ACK负载(带负载数据的ACK包)
		uint8_t EN_DPL:1;       //使能动态负载长度
		uint8_t :4;
        
	};
	uint8_t reg;
} FEATURE_Regist;

#endif
